SQCLR=0, SQMON=0, BSTS=0, ACLRM=0, INBUFM=0, PID=00, PBUSY=0, ATREPM=0, SQSET=0
PIPE4 Control Registers
| PID | Response PID 0 (00): NAK response 1 (01): BUF response (depends buffer state) 2 (10): STALL response 3 (11): STALL response |
| PBUSY | Pipe Busy 0 (0): Pipe n not in use for the transaction 1 (1): Pipe n in use for the transaction |
| SQMON | Sequence Toggle Bit Confirmation 0 (0): DATA0 1 (1): DATA1 |
| SQSET | Sequence Toggle Bit Set 0 (0): Invalid (writing 0 has no effect) 1 (1): Set the expected value for the next transaction to DATA1 |
| SQCLR | Sequence Toggle Bit Clear 0 (0): Invalid (writing 0 has no effect) 1 (1): Clear the expected value for the next transaction to DATA0 |
| ACLRM | Auto Buffer Clear Mode 0 (0): Disable 1 (1): Enable (initialize all buffers) |
| ATREPM | Auto Response Mode 0 (0): Disable auto response mode 1 (1): Enable auto response mode |
| INBUFM | Transmit Buffer Monitor 0 (0): No data to be transmitted is in the FIFO buffer 1 (1): Data to be transmitted is in the FIFO buffer |
| BSTS | Buffer Status 0 (0): Buffer access by the CPU disabled 1 (1): Buffer access by the CPU enabled |